1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device which includes an etching process for etching a silicon oxide film using a silicon nitride film as a stopper.
2. Description of the Related Art
With the miniaturization of semiconductor devices, the dimensions of the structure of a semiconductor device such as the width of transfer gates and the dimensions of a contact hole are becoming smaller and smaller. In the reduction of the dimensions, it is difficult to reduce the dimension in the direction of the thickness at the same ratio as the reduction of the dimension in the transverse direction. Therefore, the aspect ratio, which is the ratio of the dimension in the direction of the thickness of the structure of the semiconductor device to the dimension in the direction of the width, has been increased instead. As the semiconductor device becomes more minute and the aspect ratio thereof is increased further, the depth of openings and grooves which must be formed by etching in the manufacturing of the semiconductor device becomes larger than the dimension in the transverse direction.
However, the etching methods available in the prior art are inevitably accompanied by the drawback that the stable formation of openings and grooves having a depth larger than the dimension in the transverse direction is difficult, which will be described hereinafter with reference to the following examples.
Firstly, a process to open a contact hole in a memory cell array portion in a dynamic random access memory chip (referred to as a DRAM chip, hereinafter) is taken as an example. The memory cell array portion and the contact hole are generally formed as shown in FIGS. 18 through 22. The following description is in accordance with FIGS. 18 through 22.
(a) As shown in FIG. 18, after isolation regions 502 are formed on a silicon substrate 501, transfer gates 504 stacked with an offset silicon oxide film 503 are formed by conventional lithography and etching. Subsequently, a mask pattern is formed by conventional lithography, and n-type impurities are implanted into the silicon substrate 501 by ion implantation. For simplification, the resist pattern at the time of the ion implantation is not illustrated.
(b) As shown in FIG. 19, a silicon oxide film is deposited on the whole surface of a wafer by chemical vapor deposition so as to be etched in an anisotropic manner to form side walls 505.
(c) As shown in FIG. 20, mask patterns a re formed by conventional lithography, and n-type impurities and p-type impurities are implanted into the silicon substrate 501 by ion implantation. For simplification, the resist patterns at the time of the ion implantation are not illustrated.
(d) As shown in FIG. 21, after a silicon oxide film 506 is deposited, a thick silicon nitride film 507, which functions as a stopper, is deposited. Subsequently, a silicon oxide film 508 is deposited so as to be planarized by chemical mechanical polishing.
(e) As shown in FIG. 22, a contact hole pattern 509 for opening a contact hole 510 on the silicon substrate 501 is formed by conventional lithography. Then, after the silicon oxide film 508 is etched using the silicon nitride film 507 as a stopper, the contact hole 510 is opened on the silicon substrate 501 by etching the silicon nitride film 507 and the silicon oxide film 506.
In the above-described process, the width of the side walls is set in such a way that the transfer gates of a peripheral circuit portion operate as desired. Here, a problem arises: as side walls with approximately the same width as those of the peripheral circuit portion are also formed in the memory cell array portion, the silicon nitride film deposits and buries most of the spaces between the transfer gates if the width of the silicon nitride film is set in such a way that the function thereof as a stopper is given priority, which causes the etching process of the silicon oxide film to be halted before the completion thereof. On the other hand, if priority is given to the complete etching of the silicon oxide film on the silicon nitride film so that the silicon nitride film is thinned, the function thereof as a stopper is depressed, resulting in short circuiting of the contact hole with the transfer gates.
Next, a process to open a metal wiring contact hole in a DRAM chip and a logic device is given as an example. In this process, a contact hole is formed by etching a silicon oxide film using a silicon nitride film as a stopper, which must be accompanied by high selectivity of silicon oxide for silicon nitride on the bottom of the deep contact hole. However, as is reported in xe2x80x9cCharacterization of Highly Selective SiO2/Si3N4 Etching of High-Aspect-Ratio Holesxe2x80x9d (Hisataka Hayashi, Kazuaki Kurihara and Makoto Sekine, Proceedings of Symposium on Dry Process, p. 225-230, 1995), under conditions of C4F8/CO where high selectivity of silicon oxide for silicon nitride is ensured, a problem arises in that the etching rate is significantly lowered when the etching depth is increased, particularly in a fine contact hole. On the other hand, under conditions of C4F8/CO/O2 where the etching rate is not lowered even in the fine contact hole, a problem arises in that sufficient selectivity of silicon oxide for silicon nitride can not be ensured. In other words, under the conditions of high selectivity, an opening can not be easily formed, yet under the conditions where a deep contact hole can be etched, wiring readily causes short circuiting because the silicon nitride film does not function as a stopper, thereby preventing stable opening of the contact hole.
In view of the above-described problems of the conventional techniques, the present invention provides a technique for etching a silicon oxide film using a silicon nitride film as a stopper so that a contact hole is opened in a self-aligned manner, etc., which corresponds to a semiconductor with a microstructure and a high aspect ratio.
In order to solve the aforementioned problems, the present invention provides a method of manufacturing a semiconductor device including an etching process for etching a silicon oxide film using a silicon nitride film as a stopper, wherein atoms of one or more kinds selected from a group consisting of carbon and atoms whose reactivity to fluorine and oxygen is equivalent to that of carbon are implanted into said silicon nitride film by an ion implantation method before said etching process, so that selectivity of silicon oxide for silicon nitride in said etching process is increased.
The atoms whose reactivity to fluorine and oxygen is equivalent to that of carbon may include atoms selected from a group consisting of boron, phosphorus, arsenic, and antimony.
It is preferable that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted under the condition that the implantation dose of said atoms, which go beyond said silicon nitride film and reach a portion situated below said silicon nitride film, must be below the level at which the characteristics of that portion are affected.
More specifically, it is preferable that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted not only after a silicon oxide film has been deposited on the silicon nitride film for planarization, but after the silicon oxide film has been etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on transfer gates has been exposed, that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted after an organic film is formed on said silicon nitride film, and/or that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted when a wafer having said silicon nitride film is inclined at a wider angle than the apparent angle of the incident ions viewed from said silicon nitride film. When said atoms of one or more kinds are atoms of one or more kinds selected from a group consisting of boron and carbon, said ion implantation method may be an ionization sputtering method.
The above etching process is preferably for forming a contact hole. Particularly, the process has an advantage when it is used to form a contact hole between the transfer gates of a semiconductor device having a plurality of transfer gates.
Hereinafter, the present invention will be described in detail.
According to the present invention, as selectivity of silicon oxide for silicon nitride in the etching process is increased, overetching of the silicon nitride film is prevented and the silicon nitride film is allowed to function fully as a stopper, even under the condition that the silicon oxide film can be etched to the surface of the silicon nitride film deposited on minute spaces between the transfer gates of a memory cell array portion and under the condition that a high etching rate is obtainable, such as the condition that the silicon oxide film can be etched to the surface of the silicon nitride film deposited as a stopper in a deep metal wiring contact hole. In other words, the selectivity of silicon oxide for silicon nitride can be compatible with the workability of the fine contact hole having a high aspect ratio.
The reason for the increased selectivity of silicon oxide for silicon nitride in the etching process by the implantation of the atoms specified above into the silicon nitride film can be explained as follows.
As reported in xe2x80x9cMechanism of Highly Selective SiO2 to Si3N4 Etching Using C4F8+CO Plasmaxe2x80x9d (Hisataka Hayashi and Makoto Sekine, Proceedings of Symposium on Dry Process, p. 135-140, 1996), etching in the high selectivity of silicon oxide for silicon nitride is accomplished by scavenging fluorine that acts as an etchant of the silicon nitride film and a fluorocarbon polymer film using CO on a vapor phase and C supplied from CO on the surface of the silicon nitride film. It is considered that the atoms implanted into the silicon nitride film together with C supplied from the vapor phase contribute to the scavenging of fluorine, thereby allowing stable etching of the silicon oxide film using the silicon nitride film as a stopper, which is deposited on the minute spaces between the transfer gates of the memory cell array portion and on the bottom of the deep contact hole.
In other words, the above-described atoms are either carbon that scavenges fluorine, inhibits carbon supplied from the vapor phase from being removed by fluorine, and inhibits C around the surface of the silicon nitride film from being completely removed by CO or O which is generated from the silicon oxide film, or atoms whose reactivity to fluorine and oxygen is equivalent to that of carbon. The atoms which are equivalent to carbon have the dissociation energy for fluorine which is equivalent to the dissociation energy of carbon for fluorine, scavenge fluorine, and inhibit carbon supplied from the vapor phase from being removed by fluorine. Further, the atoms, whose dissociation energy for oxygen is high and whose oxides have low vapor pressure, combine easily with CO or O which is generated from the silicon oxide film, and inhibit C supplied to the silicon nitride film from the vapor phase and left around the surface of the silicon nitride film from being removed by O. The atoms that are equivalent to the carbon of this type include atoms whose dissociation energy for fluorine is from 400 to 800 kJ/mol, and whose dissociation energy for oxygen is 400 to 900 kJ/mol. Specifically, boron (whose dissociation energy for fluorine is 757 kJ/mol, and whose dissociation energy for oxygen is 808 kJ/mol), phosphorus (whose dissociation energy for fluorine is 439 kJ/mol, and whose dissociation energy for oxygen is 599.1 kJ/mol), arsenic (whose dissociation energy for fluorine is 410 kJ/mol, and whose dissociation energy for oxygen is 481 kJ/mol), and antimony (whose dissociation energy for fluorine is 439 kJ/mol, and whose dissociation energy for oxygen is 481 kJ/mol) may be included. Out of these atoms, a single atom may be used or 2 or more kinds may be combined.
The atoms specified above are referred to as the xe2x80x9cscavenger atomsxe2x80x9d, hereinafter.
Any ion implantation method is appropriate as long as it is able to implant the scavenger atoms into the silicon nitride film. The implantation dose of the scavenger atoms does not have to be over the amount that is enough for the selectivity of silicon oxide for silicon nitride to increase, which a person skilled in the art can determine without difficulty.
The increased selectivity of silicon oxide for silicon nitride in the etching process is obtained by implanting the scavenger atoms into the silicon nitride film as described above. However, depending on the structure of the semiconductor device which is being manufactured, a problem may arise in that when the scavenger atoms are implanted into the silicon nitride, the implanted scavenger atoms go beyond the silicon nitride film and reach a portion situated below the silicon nitride film, thereby affecting the characteristics of that portion. Yet, the occurrence of the above-mentioned problem can be prevented by conducting the implantation of the scavenger atoms into the silicon nitride film under the condition that the implantation dose of said scavenger atoms, which go beyond said silicon nitride film and reach the portion situated below said silicon nitride film, must be below the level at which the characteristics of that portion is affected.
Therefore, in a preferable aspect of the present invention, a manufacturing method is presented wherein implantation of scavenger atoms into a silicon nitride film is conducted under the condition that an implantation dose of said scavenger atoms, which go beyond said silicon nitride film and reach a portion situated below said silicon nitride film, must be below the level at which the characteristics of that portion are affected (also referred to as the control implantation condition, hereinafter).
This type of control implantation condition can be set by appropriately regulating parameters such as ion accelerating energy in ion implantation.
Thus, as a further preferable aspect, the present invention provides a manufacturing method wherein implantation of scavenger atoms into a silicon nitride film is conducted not only after a silicon oxide film has been deposited on the silicon nitride film for planarization but after the silicon oxide film has been etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on transfer gates has been exposed, a manufacturing method wherein implantation of scavenger atoms into a silicon nitride film is conducted after an organic film is formed on said silicon nitride film, a manufacturing method wherein implantation of scavenger atoms into a silicon nitride film is conducted when a wafer having said silicon nitride film is inclined at a wider angle than the apparent angle of the incident ions viewed from said silicon nitride film, and a manufacturing method wherein an ion implantation method is an ionization sputtering method and scavenger atoms are one or more kinds of atom selected from a group consisting of boron and carbon.
In other words, the control implantation condition described above can be easily set by adopting any of the following (1) through (4), or adopting any combination of them.
(1) A silicon oxide film is deposited on a silicon nitride film for planarization, and the silicon oxide film is etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on transfer gates is exposed.
When a silicon oxide film is deposited on a silicon nitride film for planarization and the silicon oxide film is etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on transfer gates is exposed, implantation of ions into an unexposed silicon nitride film is restricted, thereby facilitating the setting of the control implantation condition.
(2) An organic film is formed on a silicon nitride film.
Materials of the organic film includes SWK-EX2 (a trade name, manufactured by TOKYO OHKA KOGYO). Formation methods of the organic film are not particularly restricted, one of which may be by dispensing. The thickness of the organic film is set together with the parameters such as the type of the scavenger atoms and the ion accelerating energy. The organic film restricts the projected range of ions of the scavenger atoms, thereby facilitating the setting of the control implantation condition.
The formation of the organic film is preferably conducted after the silicon oxide film has been deposited on the silicon nitride film for planarization and the silicon oxide film has been etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on the transfer gates has been exposed.
(3) A wafer is inclined at a wider angle than the apparent angle of the incident ions viewed from a silicon nitride film.
The apparent angle of the incident ions viewed from the silicon nitride film means a maximum inclination by which the incident ions can be irradiated to the bottom of grooves or openings (for example, xcex8 in FIG. 7). By inclining the wafer in this manner, the distance for which the incident ions go through the silicon nitride film is extended, thereby facilitating the setting of the control implantation condition.
(4) Low energy I/I or ionization sputtering is used.
Normally, the ion accelerating energy of low energy I/I is not higher than approximately 10 keV. When the ion acceleration energy is low, the mean value and the standard deviation of the projected range of ions of the scavenger atoms are reduced, thereby facilitating the setting of the control implantation condition.
In the case of scavenger atoms where a target for an ionization sputtering method is easily obtainable, the atoms can be implanted by the ionization sputtering method. The atoms of this type include boron, carbon, and the like.
In the ionization sputtering method, it is possible to accelerate sputtering particles, which are ionized by plasma, by AC bias applied to an electrode installed on a wafer. When the AC bias is set in such a way that the maximum value of this accelerating energy is not higher than several keV, the ion accelerating energy in the ionization sputtering method can be set relatively low (for example, when the maximum value of the ion accelerating energy is set at not more than 1 keV, the projected range of ions is not more than several nm), thereby facilitating the setting of the control implantation condition.
The manufacturing methods of the present invention are preferably used for forming a contact hole. Particularly, according to the manufacturing methods of the present invention, grooves and openings with a high aspect ratio (whose depth is larger as compared to the width or the diameter) can be formed with stability by etching. Therefore, it is advantageous that the manufacturing methods of the present invention are used for forming a contact hole with a high aspect ratio, which is required particularly for a minute semiconductor device.
Further, in the manufacturing methods of the present invention, as the function of the silicon nitride film as a stopper is fully and stably utilized, it is advantageous that the semiconductor device which is being manufactured includes a plurality of transfer gates, between which a contact hole is formed. One of the example of the semiconductor devices having a plurality of transfer gates is a DRAM chip.
In the manufacturing methods of the present invention, any process used for the manufacturing methods of the semiconductor device can adopted as well as the process required for forming a contact hole. A manufacturing method of the semiconductor device including the following steps can be given as one of the examples.
(i) Transfer gates stacked with an offset silicon oxide film are formed.
(ii) After side walls are formed on the transfer gates with a silicon oxide film, a silicon nitride film, with a thickness that does not seal between the transfer gates at a point where the distance between the transfer gates is shortest, is deposited.
(iii) After a silicon oxide film is deposited and planarized, the silicon oxide film is etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on the transfer gates is exposed.
(iv) After an organic film is formed by dispensing, scavenger atoms are implanted into the silicon nitride film under the condition that the implantation dose of the scavenger atoms, which reach materials below the silicon nitride film, must be below the level at which the properties of the materials below the silicon nitride film are deteriorated.
(v) After an inter-layer insulating film is deposited, a contact hole is formed in a self-aligned manner under the condition that a minute contact hole can be etched with stability by using the silicon nitride film, into which the scavenger atoms are implanted, as a stopper.
The following step can substitute for the above step (ii).
A silicon oxide film functioning as a protective film and a polycrystalline silicon film for forming side walls are sequentially deposited.
The side walls are formed by etching the polycrystalline silicon film in an anisotropic manner using the silicon oxide film as a stopper.
Source and drain regions of transfer gate transistors are formed by implanting n-type impurities and p-type impurities, respectively, making use of the side walls serving as a mask.
The side walls are etched in an isotropic manner using the silicon oxide film as a stopper.
A silicon nitride film, with a thickness that does not seal between the transfer gates, is deposited.
The methods of the present invention can be applied to a case where a contact hole is opened in a self-aligned manner using a silicon nitride film as a stopper, which exists along a bit line and like side walls on side walls of the bit line, in relation to a silicon substrate which exists below the bit line or to a pad connected electrically to the silicon substrate, such as a case of opening a capacitor electrode contact hole of a DRAM chip. As one of the examples, a manufacturing method including the following steps in addition to the above steps (i) through (v) can be given.
(vi) The contact hole formed in (v) is buried by polycrystalline silicon and a pad is formed by etchback.
(vii) After an inter-layer insulating film is deposited, a contact hole is formed in a self-aligned manner under the condition that a minute contact hole can be etched with stability using the silicon nitride film, into which the scavenger atoms are implanted, as a stopper.
(viii) After the contact hole is buried with a bit line film and a bit line stacked with a silicon nitride film is formed, a silicon nitride film is deposited and etched back in an anisotropic manner, which forms side walls on side walls of the bit lines.
(ix) Scavenger atoms are implanted into the silicon nitride film along the bit line or into the silicon nitride film forming the side walls under the condition that the implantation dose of the scavenger atoms, which reach materials below the silicon nitride film, must be below the level at which the properties of the materials below the silicon nitride film are deteriorated.
(x) After a silicon oxide film is deposited, a contact hole is formed in a self-aligned manner under the condition that a minute contact hole can be etched with stability using the silicon nitride film, into which the scavenger atoms are implanted, as a stopper.